The present invention relates to photolithographic techniques employed in the fabrication of semiconductor devices and, more particularly, to a method of photolithography utilizing back-side exposure and non-specular reflection to provide self-alignment of device constituents.
One example of a semiconductor device where proper alignment of the device constituents is important is the thin-film field-effect transistor (FET). The source electrode, the drain electrode or both should overlap the gate electrode by a selected distance, preferably about 1-10 microns, for optimal device performance. An excessive overlap distance causes a large source/drain-to-gate (S/D-G) capacitance and in turn causes higher transistor noise and lag in imager-type devices using thin-film FETs as switching elements. Increased S/D-G capacitance may also contribute to offset-voltage errors in liquid crystal display (LCD) devices when individual picture elements (pixels) are switched between operative and inoperative states; the charge that remains in the S/D-G capacitance when the pixel is turned-off may have to be compensated to actually switch the pixel to the inoperative state. The compensating voltage required will be determined by the S/D-G capacitance and may vary from one pixel to another in a LCD device if the S/D-G capacitance varies.
Typically, the S/D-G overlap is designed to be larger than necessary to allow for photolithographic alignment errors in the photoresist mask formed during device fabrication and to ensure a sufficiently adequate overlap width to provide an acceptable contact or on-resistance. A S/D-G overlap width shorter than an optimum value may also cause the saturation drain current of the FET to fluctuate outside of acceptable limits. Thus, it is desirable to control the overlap between the S/D electrodes and the gate electrode to an optimum width that is neither too long nor too short.
One fabrication step that is critical in controlling the S/D-G overlap distance is the formation of the photoresist mask used for patterning the top insulation layer of an FET; the mask must have an optimum width and be aligned with the gate electrode to provide the optimum S/D-G overlap distance. If the mask width is too short or too long, or the mask is misaligned relative to the gate electrode, etching errors will occur when the top insulation layer is patterned and the source and drain electrodes will be misaligned relative to the gate electrode.
It is accordingly a primary object of the present invention to provide a novel method for fabricating a semiconductor device with self-aligned constituents which is not subject to the foregoing disadvantages.
It is another object of the present invention to provide a novel method for fabricating a self-aligned thin-film transistor which controls the overlap distance of the gate electrode with each of the source and drain electrodes to an optimum distance.
It is a further object of the present invention to provide a mask for fabricating a device with self-aligned constituents.
These and other objects of the invention, together with features and advantages thereof, will become apparent from the following detailed specification when read with the accompanying drawings in which like reference numerals refer to like elements.